1. Field of the Invention
The present invention relates to a power supply circuit including a boosting circuit for boosting a power supply voltage.
2. Background Art
In NAND electrically erasable programmable read-only memories (EEPROMs) including NAND flash memories, high voltages are used for operations such as writing, erasing, and reading. Such high voltages are generated by boosting circuits.
In recent years, high voltage levels have been demanded for multivalued NAND EEPROMs.
Generally, boosting circuits configured to guarantee high set voltages increase fluctuations in output voltage at low set voltages.
In NAND EEPROMs, it is necessary to generate lower set voltages in the same boosting circuits. Conventionally, it has been difficult to achieve both high boosting capability and smaller fluctuations in output voltage at a low set voltage level.
Actually, the size of a boosting circuit (e.g., the size of a capacitor composing the boosting circuit) is determined by the rising speed of a voltage.
As the set voltage increases, it is necessary to increase the size and boosting capability of the boosting circuit because a voltage has to be increased within a predetermined time. The raised voltage increases the boosting capability and thus causes large fluctuations in output voltage.
When the boosting capability is thus increased, fluctuations in output voltage further increase with a reduction in set voltage.
As described above, it is difficult to achieve both a higher rising speed of an output voltage (high boosting capability) and smaller fluctuations in output voltage.
In a conventional power supply circuit, a power supply voltage is detected by a potential detecting circuit, the detected voltage and an output voltage level-shifted by predetermined levels by a level shifter are compared with each other by a comparator, and the amplitude of a voltage (clock signal) inputted to the gate of the MOS transistor in the first stage of a clock driving boosting section is controlled based on the comparison output (for example, see Japanese Patent No. 3596130).
The configuration of the conventional power supply circuit reduces fluctuations in output voltage according to the power supply voltage when the power supply voltage fluctuates.
However, the conventional power supply circuit does not reduce fluctuations in output voltage while increasing the rising speed of an output voltage.